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dsPIC30F3014/4013

DS70138G-page 126

2010 Microchip Technology Inc.

18.3.8

SAMPLE CLOCK EDGE

CONTROL BIT

The sample clock edge (CSCKE) control bit determines

the sampling edge for the CSCK signal. If the CSCK bit

is cleared (default), data is sampled on the falling edge

of the CSCK signal. The AC-Link protocols and most

multichannel formats require that data be sampled on

the falling edge of the CSCK signal. If the CSCK bit is

set, data is sampled on the rising edge of CSCK. The

I2S protocol requires that data be sampled on the rising

edge of the CSCK signal.

18.3.9

DATA JUSTIFICATION

CONTROL BIT

In most applications, the data transfer begins one

CSCK cycle after the COFS signal is sampled active.

This is the default configuration of the DCI module. An

alternate data alignment can be selected by setting the

DJST control bit in the DCICON1 SFR. When DJST = 1,

data transfers begin during the same CSCK cycle when

the COFS signal is sampled active.

18.3.10

TRANSMIT SLOT ENABLE BITS

The TSCON SFR has control bits that are used to

enable up to 16 time slots for transmission. These con-

trol bits are the TSE<15:0> bits. The size of each time

slot is determined by the WS<3:0> word-size selection

bits and can vary up to 16 bits.

If a transmit time slot is enabled via one of the TSE bits

(TSEx = 1), the contents of the current transmit shadow

buffer location is loaded into the CSDO Shift register

and the DCI buffer control unit is incremented to point

to the next location.

During an unused transmit time slot, the CSDO pin

drives ‘0’s or is tri-stated during all disabled time slots

depending on the state of the CSDOM bit in the

DCICON1 SFR.

The data frame size in bits is determined by the chosen

data word size and the number of data word elements

in the frame. If the chosen frame size has less than

16 elements, the additional slot enable bits have no

effect.

Each transmit data word is written to the 16-bit transmit

buffer as left justified data. If the selected word size is

less than 16 bits, then the LSbs of the transmit buffer

memory have no effect on the transmitted data. The

user should write ‘0’s to the unused LSbs of each

transmit buffer location.

18.3.11

RECEIVE SLOT ENABLE BITS

The RSCON SFR contains control bits that are used to

enable up to 16 time slots for reception. These control

bits are the RSE<15:0> bits. The size of each receive

time slot is determined by the WS<3:0> word-size

selection bits and can vary from 1 to 16 bits.

If a receive time slot is enabled via one of the RSE bits

(RSEx = 1), the shift register contents are written to the

current DCI receive shadow buffer location and the buf-

fer control unit is incremented to point to the next buffer

location.

Data is not packed in the receive memory buffer loca-

tions if the selected word size is less than 16 bits. Each

received slot data word is stored in a separate 16-bit

buffer location. Data is always stored in a left justified

format in the receive memory buffer.

18.3.12

SLOT ENABLE BITS OPERATION

WITH FRAME SYNC

The TSE and RSE control bits operate in concert with

the DCI Frame Sync generator. In the Master mode, a

COFS signal is generated whenever the Frame Sync

generator is reset. In the Slave mode, the Frame Sync

generator is reset whenever a COFS pulse is received.

The TSE and RSE control bits allow up to 16 consecu-

tive time slots to be enabled for transmit or receive.

After the last enabled time slot has been transmitted/

received, the DCI stops buffering data until the next

occurring COFS pulse.

18.3.13

SYNCHRONOUS DATA

TRANSFERS

The DCI buffer control unit is incremented by one word

location whenever a given time slot has been enabled

for transmission or reception. In most cases, data input

and output transfers are synchronized, which means

that a data sample is received for a given channel at the

same time a data sample is transmitted. Therefore, the

transmit and receive buffers are filled with equal

amounts of data when a DCI interrupt is generated.

In some cases, the amount of data transmitted and

received during a data frame may not be equal. As an

example, assume a two-word data frame is used.

Furthermore, assume that data is only received during

slot #0 but is transmitted during slot #0 and slot #1. In

this case, the buffer control unit counter would be

incremented twice during a data frame but only one

receive register location would be filled with data.

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